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Also known as Very High Speed Integrated Circuit Hardware Description Language (VHSIC-HDL), VHDL is a programming language designed to describe electronic systems, although it can be used as a general-purpose parallel programming language.

The language was created for the United States Department of Defense in the 1980s. In the development of the government's Very High Speed Integrated Circuits (VHSIC) program, developers needed a standard language that could be used to describe the structure and function of integrated circuits. VHDL was designed to solve that problem, and was then further developed under the guidance of the Institute of Electrical and Electronics Engineers (IEEE), and adopted as IEEE Standard 1076, Standard VHDL Language Reference Manual, in 1987, a version usually referred to as VHDL-87.

A 1992 revision was adopted by IEEE the following year, as VHDL-93. A later revision was known as VHDL-2002.

After that, further development of the language took place among an IEEE working group and in a technical committee of Accellera, which was created to promote standards for electronic design. This led to VHDL-2008 which, as of this date in 2019, is the most current version.

VHDL is a hardware description language used to describe digital circuits and systems. Once a system has been described in VHDL, its operations can be simulated through the use of a VHDL simulator. The circuit can also be synthesized through a synthesis program, similar to a compiler, which converts the VHDL description to a gate-level description, mapping it to standard cells or field-programmable gate array (FPGA). The HDL's most commonly in use today are VHDL and SystemVerilog.

The advantages of the language are that it allows for a description of the structure of a system using familiar programming language forms. This allows the design of a system to be simulated before being manufactured so that designers can readily compare alternatives and test for correctness without the delay and expense of hardware prototyping. It also allows the detailed structure of a design to be synthesized from a more abstract specification, so that designers can concentrate on more strategic design features, reducing the time to market of the product.

VHDL projects are also multipurpose. Once created, a calculation block can be reused on other projects. Such projects are also portable. Those created for one element base can be easily ported to another. Unlike Verilog, VHDL has a full type system, allowing for more structured code.

Commercial VHDL simulators include Aldec Active-HDL, Cadence Incisive, EDA Utilities, ModelSim, Questa Advanced Simulator, Synopsys VCS-MX, and Xilinx Vivado. Free or open-source simulators include Boot, EDA Playground, FreeHDL, GHDL, Nvc, and VHDL Simili.

Topics related to the language and any versions or implementations, simulators, or tools designed to facilitate programming in VHDL are the focus of resources listed in this category, as well as any VHDL user groups, forums, tutorials, guides, or informational sites.



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