Standardized as IEEE, Verilog is a hardware description language used to model electronic systems, and in the verification of analog, digital, genetic, and mixed-signal circuits.
In 2009, Verilog was made part of SystemVerilog, a hardware description language used to design, model, simulate, test, and implement electronic systems
Hardware description languages are similar to software programming languages, as they include ways in which to describe the propagation time and signal strengths. At the time of Verilog's introduction in 1984, it proved to be a significant improvement for circuit designers, who were using graphical schematic capture software and custom software programs to document and simulate electronic circuits.
A design goal for Verilog was for it to have a syntax similar to C, a programming language that was widely used in the development of engineering software. Verilog is case-sensitive, like C, and has a basic preprocessor, although one that is less sophisticated than that of ANSI C/C++. Its control flow keywords and operator precedence are compatible with C, although there are syntactic differences.
Designed by Prabhu Goel, Phil Moorby, Chi-Lai Huang, and Douglas Warmke, Verilog was the first successful hardware description language. The original holder of the proprietary language was Automated Integrated Design Systems, which was renamed Gateway Design Automation in 1985, and purchased by Cadence Design Systems in 1990. Cadence now holds the proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would later become the de facto standard for Verilog logic simulators for the next decade.
Cadence made the language available for open standardization in 1995, transferring Verilog into the public domain under the Open Verilog International, now known as Accellera. Verilog was submitted to IEEE, becoming IEEE Standard 1364-1995, or Verilog-95. Cadence also began work on Verilog-A, obtaining standards support for Spectre, its analog simulator. Verilog-A was intended to be a subset of Verilog-AMS, which included Verilog-95.
Extensions were submitted to IEEE in 2001 and accepted as IEEE Standard 1364-2001, also known as Verilog-2001, which is an upgrade of Verilog-95, and the version supported by most commercial Electronic Design Automation (EDA) software packages.
Verilog-2005 included minor corrections, clarifications to the specifications, and a few new language features. Verilog-AMS is a separate part of the Verilog standard that attempts to integrate analog and mixed-signal modeling with traditional Verilog.
The creation of other hardware verification languages, such as OpenVera, encouraged the development of Superlog by Co-Design Automation. Later, the foundations of Superlog and Vera were acquired by Accellera, becoming the IEEE standard P1800-2005, known as SystemVerilog.
SystemVerilog is a superset of Verilog-2005 that adds several new features to assist in design verification and design modeling. In 2009, SystemVerilog and the Verilog language were merged into SystemVerilog 2009, either of which is appropriate for inclusion in this category, along with any other tools designed to facilitate the use of the language or languages, as well as user groups, forums, tutorials, or guides.
Recommended Resources
Asic World Directory: SystemVerilog
Specializing in VLSI/DIGITAL information, the site includes a tutorial on SystemVerilog that is sorted into an introduction, Verilog basics, and several chapters of instructions on the use of the hardware programming language, as well as several examples using SystemVerilog, a list of tools that are used with the language system, and recommended books pertaining to the system. Links to several Verilog and SystemVerilog online resources are included, including industry working groups.
http://www.asic-world.com/systemverilog/
Chip Verify offers tutorials on the data types, basics, and design examples of the Verilog hardware language, as well as a tutorial on SystemVerilog, which defines the language, compares it favorably to Verilog, and offers an introduction to the language, gives code examples, and offers instruction on data types, control flow, processes, communication, interface, class, constraints, constructs, and functional coverage, as well as testbench examples.
https://www.chipverify.com/
A free implementation of Verilog, Icarus Verilog is a Verilog simulation and synthesis tool that operates as a compiler, compiling source code written in Verilog into some target format. Its description and uses are put forth, along with development notes, several add-ons that can be used to extend Icarus Verilog, and links to other open-source Verilog tools and related resources. Support providers are listed, and bug reports and media data are reported on the site.
http://iverilog.icarus.com/
Established in 1997, Project VeriPage has become a resource for free information on Verilog HDL and Verilog PLI, and now includes information on SystemVerilog and DPI, as well as providing IP services for cryptographic cores. Both Verilog and SystemVerilog are covered in detail, including tutorials on various aspects of the languages, a history of the languages, and tool vendors. Verilog PLI and SystemVerilog DPI tutorials and guides are included, with code examples.
http://www.project-veripage.com/
SVUnit is a unit test framework for developers writing code in SystemVerilog, allowing users to verify SystemVerilog modules, classes, and interfaces in isolation to eliminate bugs in the design. Its features are listed and highlighted, and project activity and development notes are recorded. Hosted on SourceForge, SVUnit may be freely downloaded, and users may rate and leave reviews online. Links to support resources are posted, and an online discussion area is included.
https://svunit.sourceforge.io/
SVeN is a hyperlinked SystemVerilog BNF navigator from XtremeEDA, as published in the IEEE 1800-2012 SystemVerilog standard. Its source text includes a Library source text and SystemVerilog source text, as well as the coding for module ports, module items, configuration, interface items, program items, checker items, class items, constraints, package items, declarations, declaration types, net and variable types, strengths, delays, declaration lists, and so on.
http://sven.xtreme-eda.com/
Dedicated to Verifying Logic in general, and to Verilog in particular, the site features a page of links to the IEEE Verilog Standardization Group’s pages, along with a history and overview of the Verilog hardware descriptive language. Related topics include Verilog Mode, an open-source tool for GNU Emacs, and a request for Verilog Emacs Mode registration may be completed online. Documentation and installation instructions are included. A self-study course in Verilog is available.
http://www.verilog.com/
Featuring publicly licensed open-source software related to SystemVerilog and SystemC design and verification, Veripool was established as a repository of the author’s ASIC and electric engineering tools in 1998, and has since added several open-source tools, such as Verilator, a Verilog/SystemVerilog simulator, and Verilog-Mode, an Emacs mode for Verilog/SystemVerilog with AUTOs, as well as Verilog-Perl, a Perl Verilog/SystemVerilog language module, each of which may be downloaded.
https://www.veripool.org/
VLSIGuru: Verilog for Design and Verification
The VLSIGuru Training Institute is a VLSI and embedded systems training institute based in Bangalore. Its VG-VERILOG course is designed to enable engineers to develop their skills in Verilog constructs and issues a certificate of training completion to those who successfully complete the course. Its target audience is specified, and a syllabus, schedule, and list of course material are put forth. A trainer profile states the qualifications of the course trainer, and a demo session is available.
https://www.vlsiguru.com/verilog-training/
