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Standardized as IEEE, Verilog is a hardware description language used to model electronic systems, and in the verification of analog, digital, genetic, and mixed-signal circuits.

In 2009, Verilog was made part of SystemVerilog, a hardware description language used to design, model, simulate, test, and implement electronic systems

Hardware description languages are similar to software programming languages, as they include ways in which to describe the propagation time and signal strengths. At the time of Verilog's introduction in 1984, it proved to be a significant improvement for circuit designers, who were using graphical schematic capture software and custom software programs to document and simulate electronic circuits.

A design goal for Verilog was for it to have a syntax similar to C, a programming language that was widely used in the development of engineering software. Verilog is case-sensitive, like C, and has a basic preprocessor, although one that is less sophisticated than that of ANSI C/C++. Its control flow keywords and operator precedence are compatible with C, although there are syntactic differences.

Designed by Prabhu Goel, Phil Moorby, Chi-Lai Huang, and Douglas Warmke, Verilog was the first successful hardware description language. The original holder of the proprietary language was Automated Integrated Design Systems, which was renamed Gateway Design Automation in 1985, and purchased by Cadence Design Systems in 1990. Cadence now holds the proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would later become the de facto standard for Verilog logic simulators for the next decade.

Cadence made the language available for open standardization in 1995, transferring Verilog into the public domain under the Open Verilog International, now known as Accellera. Verilog was submitted to IEEE, becoming IEEE Standard 1364-1995, or Verilog-95. Cadence also began work on Verilog-A, obtaining standards support for Spectre, its analog simulator. Verilog-A was intended to be a subset of Verilog-AMS, which included Verilog-95.

Extensions were submitted to IEEE in 2001 and accepted as IEEE Standard 1364-2001, also known as Verilog-2001, which is an upgrade of Verilog-95, and the version supported by most commercial Electronic Design Automation (EDA) software packages.

Verilog-2005 included minor corrections, clarifications to the specifications, and a few new language features. Verilog-AMS is a separate part of the Verilog standard that attempts to integrate analog and mixed-signal modeling with traditional Verilog.

The creation of other hardware verification languages, such as OpenVera, encouraged the development of Superlog by Co-Design Automation. Later, the foundations of Superlog and Vera were acquired by Accellera, becoming the IEEE standard P1800-2005, known as SystemVerilog.

SystemVerilog is a superset of Verilog-2005 that adds several new features to assist in design verification and design modeling. In 2009, SystemVerilog and the Verilog language were merged into SystemVerilog 2009, either of which is appropriate for inclusion in this category, along with any other tools designed to facilitate the use of the language or languages, as well as user groups, forums, tutorials, or guides.



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